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Carl Poppa 🛸

January 3, 2021 at 1:15 PM

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📚 homework time...

✅ complete VPC module
✅ complete common network designs
½ complete VM labs

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Welcome to the new Makerlog!

There is still quite a bit of work to be done yet, I apologize if you expected more.

Our goal is to get it out as quickly as possible and iterate from there.

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